1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to path-based floorplan analysis.
2. Related Art
Advances in process technology and a practically unlimited appetite for consumer electronics have fueled a rapid increase in the size and complexity of integrated circuit (IC) designs. The performance of EDA tools is very important because it reduces the time to market for IC designs. Floorplanning is an important stage in an EDA design flow that involves arranging relatively large circuit blocks (e.g., macros, memories, groups of smaller logic cells, etc.) within the area allotted to the circuit design. After these circuit blocks have been arranged in the circuit design (i.e., the circuit blocks have been placed in their assigned locations in the circuit design), the logic within each circuit block can then be placed and optimized to meet circuit performance goals.
Unfortunately, due to the rapid increase in the size and complexity of IC designs, due to the stringent timing, area, and power budgets that are imposed on the IC designs, and due to the limited capabilities of conventional floorplanning tools, the floorplanning stage often takes a very long time to complete and/or produces poor quality results.